After looking at a lot of schemes, I came up with the following scheme. The input transformer makes sure that we drive the FETs with a very low impedance, which is good for stability. We probably have to experiment with the transformer to get the best results. Furthermore we use some proposals to create some feed back via the 10nF, 470 ohms network. Also for stability and linearity (which we don't need for class E, by the way. Later more about that). The network before the gate is also for stability. Nothing worse than spontaneous resonances. The Capacitor which I forgot to give a value in the scheme is by the way 100nF. Make sure the Capacitor at the end stage is 680pF 400V. It swings to quite some voltages over there. Later we will measure it to get familiar with these high voltages. The output transformer is adapting the low impedance at the drains of the FETs to an acceptable impedance at the output, which should be as close to 50ohm. We will probably need to experiment a bit with the transformer, because I read somewhere that the output impedance of the FETs is dependent on the drain DC voltage. Also the output transformer will greatly determine the efficiency of the amp.